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A comparative study of access topologies for chip-level address-event communication channels

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2 Author(s)
E. Culurciello ; Electr. & Comput. Eng. Dept., Johns Hopkins Univ., Baltimore, MD, USA ; A. G. Andreou

We examine channel access algorithms and circuits for intra and inter chip communication channels. Classical access techniques such as arbitration, scanning, ALOHA, and priority encoding are compared by assessing throughput, latency, and power consumption. Our results provide guidance in the design of bio-inspired networks of processors, for efficient transmission of information with limited power consumption and reduced latency.

Published in:

IEEE Transactions on Neural Networks  (Volume:14 ,  Issue: 5 )