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Super scalar architecture for billion device combinational and sequential circuit test design

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4 Author(s)

A number of ATPG algorithms exist for testing digital systems. ATPG being an NP complete process; application of these for testing billion device chips will be a terrible task. In general, the test generation time grows exponentially with die area. To overcome this, emulators have been proposed. But these emulation systems are targeted only towards a specific method, like serial fault simulation or combinational test generation or satisfiability. However, we propose a generalized application specific super scalar architecture for accelerated test generation and fault evaluation. This architecture is generalized in the sense that it can be programmed to perform combinational & sequential ATPG, fault evaluation and functional level testing.

Published in:

AUTOTESTCON 2003. IEEE Systems Readiness Technology Conference. Proceedings

Date of Conference:

22-25 Sept. 2003