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4-bit multiplexer/demultiplexer chip set for 40-Gbit/s optical communication systems

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8 Author(s)
K. Ishii ; NTT Photonics Labs., NTT Corp., Kanagawa, Japan ; H. Nosaka ; M. Ida ; K. Kurishima
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We have designed and fabricated a low-power 4:1 multiplexer (MUX), 1:4 demultiplexer (DEMUX) and full-clock-rate 1:4 DEMUX with a clock and data recovery (CDR) circuit using undoped-emitter InP-InGaAs HBTs. Our HBTs exhibit an fT of approximately 150 GHz and an fmax of approximately 200 GHz at a collector current density of 50 kAμm2. In the circuit design, we utilize emitter-coupled logic and current-mode logic series gate flip-flops and optimized the collector current density of each transistor to achieve low-power operation at required high bit rates. Error-free operation at bit rates of up to 50 Gbit/s were confirmed for the 4:1 MUX and 1:4 DEMUX, which dissipates 2.3 and 2.5 W, respectively. In addition, the full-clock-rate 1:4 DEMUX with the CDR achieved 40-Gbit/s error-free operation.

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IEEE Transactions on Microwave Theory and Techniques  (Volume:51 ,  Issue: 11 )