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The impact of mechanical stress caused by shallow trench isolation (STI) process in a 90 nm CMOS technology was investigated. Different stresses were monitored by utilizing various spaces between gate and STI edge and changing STI process parameters. By monitoring Idsat, 13.5% degradation with NMOS, and 23% improvement with PMOS from 2.69 to 0.26 μm space on 50 nm Si SOI substrate was observed. In case of PMOS, device with thinner Si SOI and thicker liner oxidation showed more improvement at small space which implies more stress. However, NMOS was less sensitive to the stress. NO (Nitric Oxide) liner process led to the smallest PMOS Idsat change, which is good to minimize performance variation of the circuit caused by different layouts.