Referenced Items are not available for this document.
In this paper, a new local bottom-gate configuration of CNFET is proposed. By patterning the doped top silicon film of a SOI wafer to form gates of FETs, individually addressable devices on the same substrate are realised. The thin and good quality thermal oxide is used as gate dielectric, so the supply voltage and power consumption can be reduced.
Published in:
SOI Conference, 2003. IEEE International
Date of Conference: 29 Sept.-2 Oct. 2003
- Page(s):
- 63 - 64
- ISSN :
- 1078-621X
- Print ISBN:
- 0-7803-7815-6
- INSPEC Accession Number:
- 7898610
- Digital Object Identifier :
- 10.1109/SOI.2003.1242899
- Product Type:
- Conference Publications
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