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A high-input-sensitivity (30 mV) decision D flip-flop (DFF) IC fabricated in a self-aligned InP DHBT technology is presented. Full- and half-rate phase margin at 43 Gbit/s were measured. Two optical receiver experiments using this decision DFF for 40 Gbit/s NRZ (full-rate) and 80 Gbit/s RZ (half-rate) data are also presented.
Date of Publication: 16 Oct. 2003