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Memory utilization is a vital issue in the implementation of the MAP algorithm. The MAP decoder operating in the log domain requires either the forward or the backward path metrics to be stored before finally calculating the log-likelihood decisions. This process consumes large amount of memory. In this paper, we present a reduced complexity version of a technique which computes the reverse state metrics in the forward direction and hence reduces the required memory size. A low power VLSI architecture of a log-MAP decoder employing this technique is presented. We provide results which demonstrate that the proposed design reduces the memory size and hence reduces the power consumption by 35%.