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SiGe BiCMOS PAM-4 clock and data recovery circuit for high-speed serial communications

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2 Author(s)
Ming-ta Hsieh ; Dept. of Electr. & Comput. Eng., Minnesota Univ., USA ; G. E. Sobelman

A multilevel clock and data recovery (CDR) circuit for highspeed serial data transmission was designed using the IBM 6 HP 0.25 μm SiGe BiCMOS process technology. The circuit extracts the clock from a 32 Gb/s 4-level pulse amplitude modulated (PAM-4) input signal and outputs four channels of retimed NRZ data at 8 Gb/s per channel. The CDR design incorporates a PAM-4 to 2-bit-binary converter, a phase/frequency detector, a loop filter, a quadrature LC ring oscillator and a data-retiming module. The circuit operates using a 3.3 V supply voltage with a 350 mA current consumption. The simulation results show that the peak-to-peak jitter is 1.3 ps, the capture range is 2 GHz, the acquisition time is 200 ns and the input sensitivity is 150 mV. This PAM-based CDR technique is quite suitable for low-loss transmission channels such as fiber optic communications or short-distance copper links, including network-on-chip (NOC) implementations and storage area networks (SANs).

Published in:

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Date of Conference:

17-20 Sept. 2003