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A pipelined SoPC architecture for data link layer protocol processing

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3 Author(s)
Sezer, S. ; Sch. of Electr. & Electron. Eng., Queen''s Univ., Belfast, UK ; Toal, C. ; Xing Yu

This paper presents the architecture and implementation of a 2.5 Gbps programmable data link layer protocol processor on a Virtex II FPGA. A 32 bit wide pipelined processor circuit is implemented for point-to-point protocol processing (PPP) and a Leon processor core is embedded for higher layer PPP control protocol processing. An AMBA bus interface is used to interlink the Leon processor to the hardware frame processing unit and presents a standard interface allowing easy retargeting to other processor platforms. Complex memory control is implemented to enable the microprocessor to handle control packets arriving at 2.5 Gbps. The high-level system breakdown is described and Virtex II synthesis results presented.

Published in:

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Date of Conference:

17-20 Sept. 2003

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