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ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique

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2 Author(s)
Ming-Dou Ker ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Hsin-Chyh Hsu

A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in a mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device, to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit, with the substrate-triggered technique, for a 2.5 V/3.3 V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25 μm salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased ∼60% by this substrate-triggered design.

Published in:

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Date of Conference:

17-20 Sept. 2003