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Impact of on-chip process variations performance on MCML [MOS current mode logic]

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1 Author(s)
Bruma, S. ; Philips EDT, Netherlands

The effect of on-chip process variations on MOS current mode logic (MCML) performance is explored. A closed form expression for the noise-margin is derived. On-chip process variations are shown to set the lower limit for the power dissipation of an MCML family.

Published in:

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Date of Conference:

17-20 Sept. 2003