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Comprehensively quantum mechanical effects and their impact on SOC CMOS logic circuit performance are studied, based on novel compact physical models. Significant performance degradation and power dissipation increase due to quantum mechanical effects are demonstrated in sub-100nm technologies. Specifically, 39% and 41% increase in power dissipation and device area, respectively, due to quantum effects compared with classical performance, are projected for the 25 nm technology generation. The results show that quantum effects will become a key constraint on circuit performance in future SOC technology generations.