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Design and realization of a 2.4 Gbps - 3.2 Gbps clock and data recovery circuit using deep-submicron digital CMOS technology

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2 Author(s)

This paper presents the design, verification, system integration and the physical realization of a high-speed monolithic phase-locked loop (PLL) based clock and data recovery (CDR) circuit. The architecture of the CDR has been realized as a two-loop structure consisting of coarse and fine loops, each of which is capable of processing the incoming low-speed reference clock and high-speed random data. Important features of this CDR include small area, single 1.2 V power supply, low power consumption, capability to operate at very high data rates, and the ability to handle between 2.4 Gbps and 3.2 Gbps data rate. The CDR architecture was realized using a conventional 0.13 μm digital CMOS technology, which ensures a lower overall cost and better portability for the design. The circuit is capable of operating at sampling frequencies of up to 3.2 GHz, and still can achieve robust phase alignment. The overall power consumption is estimated as 18.6 mW at a 3.2 GHz sampling rate. The overall silicon area of the CDR is approximately 0.3 mm2 including its internal loop filter capacitors.

Published in:

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Date of Conference:

17-20 Sept. 2003