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Improved Mitchell-based logarithmic multiplier for low-power DSP applications

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1 Author(s)
Mclaren, D.J. ; Inst. for Syst. Level Integration, Livingston, UK

This paper presents a method to improve the accuracy of a logarithmic multiplier, based on Mitchell's algorithms for calculating logarithms and antilogarithms. The method developed offers an area saving of approximately 50% and a power saving of 71% for larger input widths. A FIR filter based on the multiplier is also presented.

Published in:

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Date of Conference:

17-20 Sept. 2003