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In this paper, we present a novel N-controlled SRAM (NC-SRAM) design for reducing the subthreshold leakage in cache and embedded memories using a dual-Vt process. We combine the use of high Vt transistors in the leakage path and gating the supply voltage to reduce leakage in unused SRAM cells. This circuit-level technique overcomes the potential limitations in the existing techniques for reducing leakage in memory circuits. In this design, the data stored in the cell is retained even when the memory is put in the stand-by mode, with no additional complexity or circuit overhead. Simulation results indicate that NC-SRAM has better leakage savings as compared to other techniques. In addition, our results on 100 nm and 70 nm processes show 21% and 18% reduction in total power and 77% and55 % reduction in leakage power, respectively, with very minimal impact on performance and area, as compared to a conventional 6T-SRAM.
Date of Conference: 17-20 Sept. 2003