SEU-hardened resistive-load static RAMs

A charge partitioning (CP) design technique for MOS resistive-load static RAMs (RMOS SRAMs) is presented. This technique, when applied to RMOS SRAMs with specific capacitance attributes, may produce significant SEU error-rate control without sacrifices in area or power consumption. Silicon-on-insulator (SOI) technology, usually not considered appropriate for conventional RMOS SRAMs because of reduced storage capacitances, appears to be an excellent technology for CP-hardened RMOS. Simulated CP-hardened, 4-transistor RMOS RAM cells in SOI approach the error-rate performance of rad-hard, full 6-transistor CMOS cells.<
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