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A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

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7 Author(s)
Pilo, H. ; IBM Microelectron., Essex Junction, VT, USA ; Anand, D. ; Barth, J. ; Burns, S.
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This paper describes a 144-Mb DRAM that operates at a random cycle of 5.6 ns and is capable of producing data rates of 1.4 Gb/s/pin. The 121-mm2 die is fabricated in a 0.13-μm logic-based process with embedded DRAM. The cycle time is achieved using an early-write sensing technique that eliminates most of the timing overhead associated with the write cycle. Dynamic-precharge decoding in the subarray decode path is implemented to improve the access time. An improved data-formatting circuit is used to arrange the exit order of the eight-word burst. These circuit techniques produce latencies of 5.0 ns. The DRAM uses a DDR3-SRAM interface and is function and package compatible with industry-standard DDR3 SRAMs. Highlights of the DDR3 interface include the use of active termination circuitry on all inputs. The active termination improves the data-eye window and improves data capturing with minimum data setup and hold.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:38 ,  Issue: 11 )

Date of Publication:

Nov. 2003

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