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Tunnel-leakage currents become the dominant form of leakage as MOS technology advances. An electric-field-relaxation scheme that suppresses these currents is described. Cosmic-ray-induced multierrors have now become a serious problem at sea level. An alternate error checking and correction architecture for the handling of such errors is also described, along with the application of both schemes in an ultralow-power 16-Mb SRAM. A test chip fabricated by using 0.13-μm CMOS technology showed per-cell standby-current values of 16.7 fA at 25°C and 101.7 fA at 90°C. The chip provided a 99.5% reduction in soft errors under accelerated neutron-exposure testing.
Date of Publication: Nov. 2003