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Application of multilevel cell (MLC) technology to a flexible read-while-write flash memory has been achieved through the use of a highly optimized sensing architecture. The goal of this implementation is to provide performance on par with single-bit-per-cell implementations while significantly reducing the overall die size. In order to achieve the required high-speed operation using MLC structures, all offsets to the sense amplifier were minimized and the column load and local sense amplifier were optimized to provide ample differential gain. Through the use of these optimization techniques, a 1.8-V MLC-based flexible read-while-write memory with 125-MHz continuous burst and 40-ns random read access time has been manufactured. Using a 0.13-μm technology, this new device provides a die size that is 25% of the size of the equivalent single-bit-per-cell device manufactured on a 0.18-μm technology.