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A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation

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2 Author(s)
M. Mansuri ; Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA ; C. -K. K. Yang

This paper describes a fully integrated low-jitter CMOS phase-locked loop and clock buffer for low-power digital systems with a wide range of operating frequencies. The design uses static CMOS inverters as a building block of the voltage-controlled oscillator and clock buffering. To reduce supply-induced jitter, programmable circuits with opposite sensitivity compensate for the delay variations. Both elements have supply-induced delay sensitivity of ≤0.1%-delay/1%-VDD. The design is fabricated in 0.25-μm CMOS technology and consumes 10mW from a 2.5-V supply. The experimental results verify that the proposed methods significantly improve the jitter.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:38 ,  Issue: 11 )