Cart (Loading....) | Create Account
Close category search window
 

A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Mansuri, M. ; Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA ; Yang, C.-K.K.

This paper describes a fully integrated low-jitter CMOS phase-locked loop and clock buffer for low-power digital systems with a wide range of operating frequencies. The design uses static CMOS inverters as a building block of the voltage-controlled oscillator and clock buffering. To reduce supply-induced jitter, programmable circuits with opposite sensitivity compensate for the delay variations. Both elements have supply-induced delay sensitivity of ≤0.1%-delay/1%-VDD. The design is fabricated in 0.25-μm CMOS technology and consumes 10mW from a 2.5-V supply. The experimental results verify that the proposed methods significantly improve the jitter.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:38 ,  Issue: 11 )

Date of Publication:

Nov. 2003

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.