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A requirement-specific decoder design for forward error-correction in 2 Gbps optical fiber communication system is presented. Low-density parity-check codes are used to achieve high bit error rate performance. Several novel error-decoding architectures are proposed and their design configurations explored to identify optimal cost/performance design. Serial, parallel and scalable architectures are studied. The result is a scaleable architecture that consists of 1.3 million CMOS gates running at 295 MHz and it achieves a throughput of 2.51 Gbps.