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Power fluctuation minimization during behavioral synthesis using ILP-based datapath scheduling

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3 Author(s)
S. P. Mohanty ; Dept. of CSE, Univ. of South Florida, Tampa, FL, USA ; N. Ranganathan ; S. K. Chappidi

We model the power fluctuation as cycle-to-cycle power gradient and minimize the mean of the power gradients using ILP. We propose scheduling schemes for three modes of datapath design: single supply voltage and single frequency (SVSF), multiple supply voltages and dynamic frequency clocking (MVDFC), and multiple supply voltages and multicycling (MVMC). Various experiments are conducted on selected high-level synthesis benchmarks. Experimental results in terms of several parameters, such as mean power gradient, mean cycle power, peak power, and power delay product, are presented.

Published in:

Computer Design, 2003. Proceedings. 21st International Conference on

Date of Conference:

13-15 Oct. 2003