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Multiple-Vdd scheduling/allocation for partitioned floorplan

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3 Author(s)
Kang, D. ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Johnson, M.C. ; Roy, K.

We propose a multiple-Vdd scheduling and allocation scheme for low-power that considers a partitioned floorplan. Multiple-Vdd designs inevitably introduce an additional power mesh, thus consuming an additional metal layer. Considering voltage partition during scheduling, we may place the resources of same voltage in one partition; thereby reducing the additional power meshes. Such a schedule can also reduce the interfaces between different voltage partitions. Therefore, the logic level-converters and the interconnects can be reduced. To accomplish this, we first generate a multiple-Vdd schedule using force-directed scheduling. Given resource and time constraints, the multiple-Vdd scheduler determines the voltage assignment of each node with resource constraints. Next, voltage partitioning is performed. Based on pair-wise and multiple-way graph partitioning, the voltage partitioning algorithm iteratively improves the schedule and the allocation. The proposed scheme generates a multiple-Vdd schedule for an improved voltage partitioned floorplan. Reduction of level-converter cost, interconnect cost, and the number of voltage clusters were achieved. Relative to the minimum single voltage design, the average energy savings of a multiple-Vdd partitioned design was 29.7%. Reductions of 33.1%, 28.3%, 51.3% were achieved for level-conversion energy, total bus length and interconnect energy, respectively.

Published in:

Computer Design, 2003. Proceedings. 21st International Conference on

Date of Conference:

13-15 Oct. 2003