Interconnect estimation for FPGAs under timing driven domains

Interconnect planning is fast becoming an important design issue for large FPGA based designs. The fundamental requirement for interconnect planning is the ability to estimate the routing requirements of a given design. Many estimation methods for uniform island-style FPGA architectures have been reported. However, no estimation method targets the problem of estimating the interconnect requirements for timing driven physical design. Most estimation methods assume minimum cost routing, which underestimates the interconnect resource requirements when timing is of main concern. Timing driven physical design typically involves minimum delay routing which demands extra interconnects as compared to minimum-cost routing. We propose a new method to estimate the interconnect requirements of placed FPGA circuits, under timing driven domains. We compare our estimates with the detailed routing results produced by standard routing tools in the VPR [V. Betz et al., (1997)] design suite.