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In order to achieve multi-GHz operation frequency for VLSI design, clock networks need to be designed in a very elaborated manner and be able to deliver prescribed useful skews rather than merely zero-skew. Although traditional zero-skew clock muting methods can be extended directly to prescribed skews, they tend to result in excessive wirelength as the differences among delay-targets for clock sinks are neglected. In this paper, we propose the maximum delay-target and minimum merging-cost merging scheme for prescribed-skew clock routing. This scheme is simple yet surprisingly effective on wirelength reduction. Experimental results on benchmark circuits show that our merging scheme yields 53%-61% wirelength reduction compared to traditional clock routing methods.