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A mixed-mode delay-locked-loop architecture

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3 Author(s)
Eckerbert, D. ; Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden ; Svensson, L.J. ; Larsson-Edefors, P.

We present a mixed-mode delay-locked loop (DLL) architecture intended for multiple-phase clock generation. In contrast to analog DLLs, the proposed architecture allows for clock-gating; moreover, circuit simulations indicate that its performance (in terms of maximum frequency, frequency range, and low-speed power dissipation) is superior to that of a previously-reported, purely digital DLL.

Published in:

Computer Design, 2003. Proceedings. 21st International Conference on

Date of Conference:

13-15 Oct. 2003