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We present a satisfiability-based algorithm for automatically generating test sequences that target gate-level stuck-at faults in a circuit by using its register-transfer level (RTL) description. Our methodology exploits a popular, unified RTL circuit representation, called assignment decision diagrams, for its analysis and justifies module-level precomputed test vectors on this representation. Test generation proceeds by abstracting the components in this unified representation using input/output propagation rules, so that any justification/propagation event can be captured as a Boolean implication. Consequently, we reduce RTL test generation to a satisfiability (SAT) instance that has a significantly lower complexity than the equivalent problem at the gate-level. Using the state-of-the-art SAT solver ZCHAFF, we show that our RTL test generator can outperform gate-level sequential automatic test pattern generation (ATPG) in terms of both fault coverage and test generation time (two-to-three orders of magnitude speed-up), in comparable test application times. Furthermore, we show that in a bi-level testing scenario, in which RTL ATPG is followed by gate-level sequential ATPG on the remaining faults, we improve the fault coverage even further, while maintaining a high speed-up in test generation time (nearly 29X) over pure gate-level sequential ATPG, at comparable test application times.