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Low power adder with adaptive supply voltage

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3 Author(s)
H. Suzuki ; Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; W. Jeong ; Kaushik Roy

Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a low power adder, which adoptively selects supply voltages based on the input vector patterns. We prototyped a 32-bit Ripple Carry Adder and analyzed the power consumption and performance in details. Results show 29% improvement in power consumption over a conventional ripple carry adder with comparable performance.

Published in:

Computer Design, 2003. Proceedings. 21st International Conference on

Date of Conference:

13-15 Oct. 2003