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Procedural level address offset assignment of DSP applications with loops

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2 Author(s)
Youtao Zhang ; Dept. of Comput. Sci., Texas Univ., Richardson, TX ; Yang, J.

Automatic optimization of address offset assignment for DSP applications, which reduces the number of address arithmetic instructions to meet the tight memory size restrictions and performance requirements, received a lot of attention in recent years. However, most of current research focuses at the basic block level and does not distinguish different program structures, especially loops. Moreover, the effectiveness of modify register (MR) is not fully exploited since it is used only in the post optimization step. A novel address offset assignment approach is proposed at the procedural level. The MR is effectively used in the address assignment for loop structures. By taking advantage of MR, variables accessed in sequence within a loop are assigned to memory words of equal distances. Both static and dynamic addressing instruction counts are greatly reduced. For DSPSTONE benchmarks and on average, 9.9%, 17.1% and 21.8% improvements are achieved over address offset assignment [R. Leupers et al., (1996)] together with MR optimization when there is 1, 2 and 4 address registers respectively

Published in:

Parallel Processing, 2003. Proceedings. 2003 International Conference on

Date of Conference:

9-9 Oct. 2003