By Topic

An efficient BIST method for non-traditional faults of embedded memory arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
W. -B. Jone ; Sch. of Inf. Technol. & Eng., Univ. of Ottawa, Ont., Canada ; Der-Chen Huang ; S. R. Das

In this work, a built-in self-testing (BIST) method is proposed to detect nontraditional faults of embedded memory arrays for a system-on-chip (SoC) design. The nontraditional faults include single-cell read-sensitive faults and read coupling faults. The BIST method can efficiently deal with embedded memory arrays spatially distributed on the entire SoC chip. The concept of redundant read-write operations is applied to detect all embedded memory arrays with different sizes simultaneously. The redundant operations do not affect the fault coverage of all nontraditional faults discussed in this paper. The method has the advantages of low hardware overhead, short test time, and high fault coverage for nontraditional memory defects.

Published in:

IEEE Transactions on Instrumentation and Measurement  (Volume:52 ,  Issue: 5 )