Skip to Main Content
Space compaction of test responses provides parallel access to functional outputs and reduces testing time and test data volume. We present a new space compaction approach that only uses information about the fault-free responses for a precomputed test set T. It is, therefore, especially suitable for embedded cores. It does not make any assumption about an underlying fault model, and it does not make use of any structural information about the core. Advantages of this approach include complete error propagation for all errors and optimum (provably maximum) compaction ratio. Classical linear space compactors often require structural information and can only guarantee error propagation for a specific fault model. In contrast, the proposed compactor design is based on the use of orthogonal transmission functions, which allow all errors produced by T to be propagated through the space compactor. We illustrate the proposed method by presenting case studies on compactor synthesis for several large ISCAS benchmark circuits. We show that maximum compaction with low area overhead can be achieved for circuits for which compact test sets are available.