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On-chip interconnect modeling by wire duplication

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3 Author(s)
Guoan Zhong ; Electr. & Comput. Eng. Dept., Purdue Univ., West Lafayette, IN, USA ; Cheng-Kok Koh ; Roy, K.

The authors present a novel wire duplication-based interconnect modeling technique. The proposed modeling technique exploits the sparsity of the L-1 matrix, where L is the inductance matrix, and constructs a sparse and stable equivalent circuit by windowing the original inductance matrix. The resulting circuit model is sparse and exhibits the same stability property as the K method. Numerical results show that the proposed wire duplication model has high accuracy and is more efficient than many existing techniques.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:22 ,  Issue: 11 )