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Limits to binary logic switch scaling - a gedanken model

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4 Author(s)
Zhirnov, V.V. ; Semicond. Res. Corp., Res. Triangle Park, NC, USA ; Cavin, R.K. ; Hutchby, J.A. ; Bourianoff, G.I.

In this paper we consider device scaling and speed limitations on irreversible von Neumann computing that are derived from the requirement of "least energy computation." We consider computational systems whose material realizations utilize electrons and energy barriers to represent and manipulate their binary representations of state.

Published in:

Proceedings of the IEEE  (Volume:91 ,  Issue: 11 )