Cart (Loading....) | Create Account
Close category search window
 

Design guideline for minimum channel length in silicon-on-insulator (SOI) MOSFET

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kawamoto, A. ; High-Technol. Res. Center/ORDIST & Graduate Sch. of Electron., Kansai Univ., Osaka, Japan ; Mitsuda, H. ; Omura, Y.

This brief proposes a preliminary design guideline for the minimum channel length in silicon-on-insulator (SOI) MOSFETs that is based on simulations of device characteristics. The simulations examine a wide variation in many device parameters to comprehensively evaluate device characteristics. A characteristic parameter that can successfully describe the minimum channel length is found. It is suggested that a sub-20-nm-channel single-gate SOI MOSFET with suppressed short-channel effects can be stably realized by optimizing its device parameters.

Published in:

Electron Devices, IEEE Transactions on  (Volume:50 ,  Issue: 11 )

Date of Publication:

Nov. 2003

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.