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Design guideline for minimum channel length in silicon-on-insulator (SOI) MOSFET

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3 Author(s)
A. Kawamoto ; High-Technol. Res. Center/ORDIST & Graduate Sch. of Electron., Kansai Univ., Osaka, Japan ; H. Mitsuda ; Y. Omura

This brief proposes a preliminary design guideline for the minimum channel length in silicon-on-insulator (SOI) MOSFETs that is based on simulations of device characteristics. The simulations examine a wide variation in many device parameters to comprehensively evaluate device characteristics. A characteristic parameter that can successfully describe the minimum channel length is found. It is suggested that a sub-20-nm-channel single-gate SOI MOSFET with suppressed short-channel effects can be stably realized by optimizing its device parameters.

Published in:

IEEE Transactions on Electron Devices  (Volume:50 ,  Issue: 11 )