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A low power turbo decoder architecture

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2 Author(s)
Elassal, M. ; Center for Adv. Comput. Studies, Univ. of Louisiana at Lafayette, LA, USA ; Bayoumi, M.

A new method is proposed to decrease the power consumption of turbo decoders. Turbo decoders iteratively decode the received sequence by exchanging extrinsic information. In the proposed method, the exchange of extrinsic information that exceeds a certain threshold is terminated and, instead, a predefined value is exchanged. This method enables reduction of memory accesses to both the interleaver memory and state metric memory, hence reducting power consumption. Simulation and synthesis results shows up to 25% reduction of power consumption at Eb/NO of 1.5 dB, compared to the conventional state parallel architecture.

Published in:

Signal Processing Systems, 2003. SIPS 2003. IEEE Workshop on

Date of Conference:

27-29 Aug. 2003