By Topic

Hardware-software codesign of a 14.4 MBit - 64 state - Viterbi decoder for an application-specific digital signal processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
M. Hosemann ; Vodafone Chair Mobile Commun. Syst., Dresden Univ. of Technol., Germany ; R. Habendorf ; G. P. Fettweis

Viterbi decoders are employed frequently in wireless radio systems. They often require high computational power which can only be handled by dedicated application specific integrated circuits (ASICs). Because of their flexibility and speed of development, DSP-based software solutions are desirable, however. Currently available DSPs are unable to provide enough computational power to perform as the Viterbi decoder in systems such as digital video broadcasting (DVB) where a DSP needs to perform 64-state Viterbi decoding at 4-30 MBit/s as well as other receiver algorithms. Hence, we strive to provide ways of increasing DSP computational power. One way is to provide multiple, parallel, data paths in a processor. Two different methods of parallel computation of a Viterbi decoder are presented and their DSP architecture requirements are analyzed. These methods are not only applicable for the Viterbi decoder in DVB systems, but for all terminated convolutional codes. We then derive a data path design for a highly parallel DSP. We introduce special instructions which not only speed up the computation of Viterbi decoders, but are also beneficial for computing a fast Fourier transform. This data path design can calculate an add-compare-select butterfly in two cycles and thus allows the DSP to perform the computation of the Viterbi decoder for the current German variant of DVB-T (14.4 Mbit/s) at a modest 70 MIPS. This leaves enough computational power to perform other receiver algorithms at a targeted clock rate of 200 MHz.

Published in:

Signal Processing Systems, 2003. SIPS 2003. IEEE Workshop on

Date of Conference:

27-29 Aug. 2003