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Reduction of coupling effects by optimizing the 3-D configuration of the routing grid

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4 Author(s)
Sakai, A. ; Mater. & Devices Dev. Center BU, Sanyo Electr. Co. Ltd., Gifu, Japan ; Yamada, T. ; Matsushita, Y. ; Yasuura, H.

In this brief, we propose a new physical design technique for a subquarter micrometer system-on-a-chip (SoC). By optimizing the individual layer's routing grid space, coupling effects such as crosstalk noise, crosstalk-induced delay variations, and coupling power consumption are almost eliminated with little runtime penalty. Experiments are performed on the design of an image processing circuit using a subquarter micron CMOS process with multilayer interconnects. Simply by employing our proposed technique, the maximum delay and the power consumption can be decreased simultaneously by up to 15% and 10%, respectively, without any other process improvements.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:11 ,  Issue: 5 )