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A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST

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16 Author(s)
Sakakibara, H. ; Device Dev. Center, Hitachi, Japan ; Nakayama, M. ; Kusunoki, M. ; Kurita, K.
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A 750MHz 144Mb cache DRAM LSI incorporates speed-scalable embedded DRAM and SRAM macros, and is realized using a logic-merged DRAM process. The LSI has a built-in at-speed test engine with programmable test pattern and timing, merging logic and memory test. The die area is 285mm/sup 2/ in a 0.18/spl mu/m 6M logic-merged DRAM process.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003

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