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A digital-to-phase converter (DPC) generates a 125MHz clock with phase shift controlled by an 8b digital input. Averaging resistor rings are used for phase interpolation and phase error reduction by averaging. Implemented in a standard 0.35 /spl mu/m CMOS technology, the DPC achieves /spl plusmn/1 LSB differential nonlinearity and /spl plusmn/2 LSB integral nonlinearity. Power dissipation is 110mW with a 3.3V supply.