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A low-power low-jitter adaptive-bandwidth PLL and clock buffer

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2 Author(s)
Mansuri, M. ; California Univ., Los Angeles, CA, USA ; Chih-Kong Ken Yang

A multi-context programmable on-chip communication network is implemented using a matrix of Flash-EEPROM pass-transistor switches (FPT) in a 0.18/spl mu/m technology. The prototype 8-context, 8/spl times/8 64b crossbar includes 576k FPT and >8k bi-directional tristate repeaters in an area of 1.38mm/sup 2/. Based on 2/spl times/2 building blocks, wave pipelining and elastic interconnect, data is transferred at 6.4Gb/s per channel, with independent clocks at both ends.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003