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A replica-biased 50% duty cycle PLL architecture with 1/spl times/ VCO

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4 Author(s)
Kurd, N. ; Intel Corp., Hillsboro, OR, USA ; Griffin, J. ; Barkatullah, J. ; Young, I.

A replica-biased PLL providing wider-frequency-range lower-power consumption and improved clock jitter and loop stability, is fabricated in 0.13/spl mu/m CMOS technology. A wide common-mode input range, matched-current amplifier provides a stable duty cycle at all operating conditions. In comparison of 1/spl times/ and 2/spl times/ VCO architecture, the 1/spl times/ VCO shows improved core timing.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003