A replica-biased 50% duty cycle PLL architecture with 1/spl times/ VCO

A replica-biased PLL providing wider-frequency-range lower-power consumption and improved clock jitter and loop stability, is fabricated in 0.13/spl mu/m CMOS technology. A wide common-mode input range, matched-current amplifier provides a stable duty cycle at all operating conditions. In comparison of 1/spl times/ and 2/spl times/ VCO architecture, the 1/spl times/ VCO shows improved core timing.