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A 1.8 V 128 Mb 125 MHz multi-level cell flash memory with flexible read while write

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32 Author(s)

A 128 Mb flash memory with a two bit-per-cell design on a 0.13 /spl mu/m technology achieves a random access time of 55 ns and 125 MHz synchronous operation. The design incorporates a flexible multi-partition memory architecture which allows a program or erase operation to occur in one partition of the memory while bursting data out of another partition. The die is 27.3 mm/sup 2/ with a 0.154 /spl mu/m/sup 2/ cell size.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003