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A 600 MHz NT3 network processor

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7 Author(s)
McMahan, S. ; NPU Eng., Cisco Syst., Richardson, TX, USA ; Erickson, B. ; McMahon, S. ; Huxel, J.
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A 97M transistor custom-designed network processor integrating 16 VLIW CPUs implements the Cisco Toaster instruction set at 600 MHz in a 0.18 /spl mu/m process. The chip area is 349 mm/sup 2/ and consumes 20 W at 500 MHz. The frequency is 2.5/spl times/ that of an ASIC Toaster implementation in a similar process.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003

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