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A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18/spl mu/m CMOS technology

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7 Author(s)
van de Beek, R.C.H. ; IC-Design Group, Twente Univ., Enschede, Netherlands ; Vaucher, C.S. ; Leenaerts, D.M.W. ; Pavlovic, N.
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A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003