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A wire-delay scalable microprocessor architecture for high performance systems

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9 Author(s)
S. W. Keckler ; Dept. of Comput. Sci., Texas Univ., Austin, TX, USA ; D. Burger ; C. R. Moore ; R. Nagarajan
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This scalable processor architecture consists of chained ALUs to minimize the physical distance between dependent instructions, thus mitigating the effect of long on-chip wire delays. Simulation studies demonstrate 1.3-15/spl times/ more instructions per clock than conventional superscalar architectures.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003