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A 13.3Mb/s 0.35/spl mu/m CMOS analog turbo decoder IC with a configurable interleaver

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2 Author(s)
V. C. Gaudet ; Toronto Univ., Ont., Canada ; P. G. Gulak

A 0.35/spl mu/m CMOS analog decoder for a 4-state, rate 1/3, block length 16 turbo code operates at 13.3Mb/s and latency of 1.2/spl mu/s and consumes 13.9nJ per decoded bit with a 3.3V supply. The 1.42mm/sup 2/ core IC implements two logarithmic domain MAP decoders and a fully programmable analog interleaver that is configured at power-up.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003