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A single-chip 802.11a MAC/PHY with a 32 b RISC processor

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16 Author(s)
Fujisawa, T. ; Toshiba Corp. Semicond., Kawasaki, Japan ; Hasegawa, J. ; Tsuchie, K. ; Shiozawa, T.
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An 802.11a compliant MAC/PHY processing chip has been successfully fabricated in 0.18 /spl mu/m CMOS. Thirty million transistors are integrated on a 10.91 /spl times/ 10.91 mm/sup 2/ die in a 361-pin PFBGA. The MAC functions are fully implemented by firmware on an embedded 32 b RISC processor and hardware acceleration logic. The PHY supports a complete set of data rates up to 54 Mb/s.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003