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Dynamic-sleep transistor and body bias for active leakage power control of microprocessors

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6 Author(s)
J. Tschanz ; Intel Corp., Hillsboro, OR, USA ; S. Narendra ; Yibin Ye ; B. Bloechel
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Sleep transistors and body bias are used to control active leakage for a 32b integer execution core implemented in a 100nm dual V, CMOS technology. A PMOS sleep transistor degrades performance by 4% but offers 20/spl times/ leakage reduction which is further improved with body bias. Time constants for leakage convergence range from 30ns to 300ns allowing 9-44% power savings for idle periods greater than 100 clock cycles.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003