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A 2.7 Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems

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5 Author(s)
Zhiwei Xu ; California Univ., Los Angeles, CA, USA ; Hyunchol Shin ; Jongsun Kim ; Chang, M.F.
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A 2.7 Gb/s interconnect transceiver chip-set based on Code Division Multiple Access (CDMA) is described and implemented in 0.18 /spl mu/m CMOS technology to achieve real-time system re-configurability and multiple I/O communication. The transceiver chip-set, with an Alexander-type multi-level data recovery circuit, can reconfigure multiple I/O signal routes within a symbol period of 0.8 ns. The chip-set dissipates 74 mW and occupies 0.3 mm/sup 2/ per I/O pair.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003