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A /spl Sigma//spl Delta/ ADC with a fifth-order continuous-time complex loop filter achieves 76dB of DNR in a 1MHz channel. The input impedance is less than 400/spl Omega/ and allows operation with a current-mode RF front-end. Image rejection is over 50dB, and IM3 distortion is below -82dBc. The circuit dissipates 4.4mW and is implemented in 0.18/spl mu/m CMOS.